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stm32stm32f4

Is there a trade-off for memory to memory DMA transfer when the data size is small?

I am learning about the STM32 F4 microcontroller. I'm trying to find out about limitations for using DMA.

Per my understanding and research, I know that if the data size is small (that is, the device uses DMA to generate or consume a small amount of data), the overhead is increased because DMA transfer requires the DMA controller to perform operations, thereby unnecessarily increasing system cost.

I did some reaserch and found the following:

Limitation of DMA

CPU puts all its lines at high impedance state so that the DMA controller can then transfer data directly between device and memory without CPU intervention. Clearly, it is more suitable for device with high data transfer rates like a disk. Over a serial interface, data is transferred one bit at a time which makes it slow to use DMA.

Is that correct? What else do I need to know?

Solution

  • As @Vinci and @0___________ (f.k.a. @P__J__) already pointed out,

    1. A DMA controller works autonomously and doesn't create overhead on the CPU it supplements (at least not by itself). But:

    2. The CPU/software must perform some instructions to configure the DMA and to trigger it or have it triggered by some peripheral. For this, it needs CPU time and program memory space (usually ROM). Besides, it usually needs some additional RAM in variables to manage the software around the DMA.

      Hence, you are right, using a DMA comes with some kinds of overhead.

    And furthermore,

    1. The DMA transfers make use of the memory bus(es) that connect the involved memories/registers/peripherals to the DMA controller. That is, while the DMA controller does its own work, it may cause the CPU which it tries to offload to stall in the meantime, at least for short moments when the data words are transferred (which in turn sum up for longer transfers...).

    On the other hand, a DMA doesn't only help you to reduce the CPU load (regarding total CPU time to implement some feature). If used "in a smart way", it helps you to reduce software latencies to implement different functions because one part of the implementation can be "hidden" behind the DMA-driven data transfer of another part (unless, both rely on the same bus resources - see above...).