How are the parameters passed from the parent makefile to the child makefile during cross compilation process? All the children modules might not be using the entire toolchain within their own makefiles but some parts of it only. How does the parent pass on these cross compiler information such as CC ranlib, ar and others to the children makefiles at the time of their individual invocations. Also how do I come to know if I am using Cmake or qmake. I am knew to this area. Any links or code snippets could be helpful.
For normal variables which are set in a makefile, like FOO = bar, they are not passed down to sub-makes at all.
If you mark a normal variable as exported (via export FOO) then they will be passed to submakes in the environment like any other environment variable. Note that assignments in the submake makefile like FOO = baz will take precedence over any value obtained from the environment.
For variables that are set on the command line, like make FOO=bar, they are passed down through the special MAKEFLAGS variable and they will take precedence over any variables set in the submake.
For the latter, though, be aware that when you invoke a sub-make you should always use the $(MAKE) variable (or ${MAKE}, same thing) and never use bare make like make.
See the docs on recursive use of make.