endfile not detected in the VHDL testbench in modelsim, the testbench just keeps repeating it self indefinetly

Question

I wrote a VHDL code that should loop through a file and close the file and stop after the file ends and closes the file but it just keeps looping indefinitely reading from the file

            FILE f               : TEXT;
            constant filename    : string :="input.txt";
            VARIABLE L           : LINE;
            variable al          : integer ;
            variable opcode_str  : string(5 downto 1);
            variable comma       : character;

            begin
            File_Open (f,FILENAME, read_mode);  
                while not endfile(f) loop
                readline (f, l);
                read(l, opcode_str);
                read(l, comma);
                read(l, Al);
                op_code<= read_opcode(opcode_str);      
                w_tb <=std_logic_vector(to_unsigned(Al, w_tb'length));
                  wait for 10 ns;
            end loop;
            File_Close (f);
        end process

Answer 1

Your process has no wait statement at the end of the process. All processes with no sensitivity list are infinite loops.

Simply add the statement

wait;  -- waits forever

at the end of the process.