VHDL No drivers exist on out port

Question

I am doing my first project in VHDL, I try to implement 8-bit barrel shifter using mux.

This is code for one block (8 mux in chain):

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.sample_package.all;
-------------------------------------
ENTITY Shifter IS
  GENERIC (n : INTEGER );
  PORT (    x,y: IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
            redB: IN Integer;
            out_m: OUT STD_LOGIC_VECTOR(n-1 downto 0));
END Shifter;
--------------------------------------------------------------
ARCHITECTURE dfl OF Shifter IS
SIGNAL sm : STD_LOGIC;
SIGNAL what_b : STD_LOGIC;
BEGIN   
  --redB in the number of the red block in the diagram
  --The first mux port map is the same for all three blocks
  sm <= y(redB); 
    first : MUX port map(
            a => x(0),
            b => '0',
            s0 => sm,
            y => out_m(0)
    );

    b0: if redB=0 generate                             --First block - only the first mux has b=0
    rest : for i in 1 to n-1 generate
          chain : MUX port map(
            a => x(i),
            b => x(i-1),
            s0 => sm,
            y => out_m(i)
          );
     end generate;
    end generate;

    b1: if redB=1 generate 
    rest : for i in 1 to n-1 generate
        what_b <= '0' when i=1 else                    --Second block - 2 first mux has b=0
                      x(i-2);                                              
          chain : MUX port map(
            a => x(i),
            b => what_b,
            s0 => sm,
            y => out_m(i)
          );
     end generate;
    end generate;

    b2: if redB=2 generate 
    rest : for i in 1 to n-1 generate
       what_b <= '0' when i=1 or i=2 or i=3 else       --Third block - 4 first mux has b=0  
                 x(i-4);
          chain : MUX port map(
            a => x(i),
            b => what_b,
            s0 => sm,
            y => out_m(i)
          );
     end generate;
    end generate;

END dfl;

In this is the code for changing 3 shifters:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.sample_package.all;

-------------------------------------
ENTITY Barrel IS
  GENERIC (n : INTEGER);
  PORT (    x,y: IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
            out_shifter0,out_shifter1,out_shifter2: OUT STD_LOGIC_VECTOR(n-1 downto 0));
END Barrel;
--------------------------------------------------------------
ARCHITECTURE dfl OF Barrel IS
SIGNAL temp_out0 : std_logic_vector(n-1 DOWNTO 0);
SIGNAL temp_out1 : std_logic_vector(n-1 DOWNTO 0);
SIGNAL temp_out2 : std_logic_vector(n-1 DOWNTO 0);
BEGIN

  y0: Shifter GENERIC MAP(n) port map (x=>x,y=>y,redB=>0,out_m=>temp_out0);
  out_shifter0 <= temp_out0;
  y1: Shifter GENERIC MAP(n) port map (x=>temp_out0,y=>y,redB=>1,out_m=>temp_out1);
  out_shifter1 <= temp_out1;
  y2: Shifter GENERIC MAP(n) port map (x=>temp_out1,y=>y,redB=>2,out_m=>temp_out2);
  out_shifter2 <= temp_out2;

END dfl;

All the files are compiling, but when I try to run a simulation I get this warning:

# ** Warning: (vsim-8684) No drivers exist on out port /tb/L0/y1/out_m(7 downto 1), and its initial value is not used.
# 
# Therefore, simulation behavior may occur that is not in compliance with
# 
# the VHDL standard as the initial values come from the base signal /tb/L0/temp_out1(7 downto 1).

I am using ModelSim. Anyone got any idea of what could be the problem?

Thanks!

Answer 1

You have done a generate with a signal, and compared its value to something. Integers initialise to -2^31, so none of the generate blocks exist because the values you have assigned externally do not get assigned until after the simulation is started, but the generates get created during elaboration (before the simulation starts) using the initial value of redB. Hence no drivers for out_m. Instead of using a signal in the generate condition, use generics instead, as their values are fixed and assigned during elaboration.