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makefiledependenciestarget

Target dependency: Makefile no rule to make target error

Here is the make file that I am running, 

.PHONY: build
build: pre_build_script $(OUTPUTDIR)/%.cpp

$(OUTPUTDIR)/%.cpp: $(INTXTDIR)/%.txt
    python.exe $(SOMEDIR)/somepythonscript.py $(INTXTDIR) $(OUTPUTDIR) 

.PHONY: pre_build_script
pre_build_script:
    pythonscript.exe $(PREBUILDDIR)

This is the output that I get:

$ make build
  pythonscript.exe $(SAMPLEDIR)
  make: *** No rule to make target '../obj/CPP/%.cpp', needed by 'build'.  Stop.

Looks like I'm missing on some sytanx as I get this error inspite of declaring the target dependency. Any suggestions?

Solution

  • This means make cannot find a file named $(OUTPUTDIR)/%.cpp, a prerequisite for the first rule.

    You cannot use % as a wildcard anywhere in a rules like this:

     build: pre_build_script $(OUTPUTDIR)/%.cpp

    it needs to be a part of pattern rule or a static pattern rule.

    You can use $(wildcard $(OUTPUTDIR)/*.cpp) to get a complete list of files, but it's an anti-pattern (pun intended). You are supposed to either exactly know what files are used in what rules, or (know it even better and) create a generic pattern rule.

    The second pattern rule (one using somepythonscript.py) is supposed to work on a single source-target file pair, $(INTXTDIR)/%.txt -> $(OUTPUTDIR)/%.cpp. The command seems to process all the files in the directory, which is not incremental: it will redo all the work even if only one file was updated.