Makefile not processing all commands

Question

I am trying to convert a hello.c to hello stepwise by first preprocessing then compiling, then assembling then linking. However only the first command of my makefile is being executed:

Osheens-MacBook-Air-1115:Assignment0.1 osheensachdev$ ls
hello.c     makefile
Osheens-MacBook-Air-1115:Assignment0.1 osheensachdev$ cat makefile

hello.i : hello.c
    gcc -E hello.c -o hello.i

hello.s : hello.i
    gcc -S hello.i -o hello.s

hello.o : hello.s
    gcc -c hello.s -o hello.o

hello : hello.o
    $ld hello.o -e main hello

clean:
    rm hello.i hello.s hello.o hello
Osheens-MacBook-Air-1115:Assignment0.1 osheensachdev$ make
gcc -E hello.c -o hello.i
Osheens-MacBook-Air-1115:Assignment0.1 osheensachdev$ make
make: `hello.i' is up to date.

I've searched online about chained files and didn't find anything specific about why this shouldn't work.

I've also specified the target: [dependancies] so I don't see why this shouldn't work.

Answer 1

The first target of a Makefile is the default target.

This is why you see in many Makefiles a all target at the top which is intended to "make everything":

all: build test

build: <prerequisites>

test: <prerequisites>

Since you didn't specify one, Make builds hello.i only (plus everything needed to build this target):

1. hello.i doesn't exist yet.
2. hello.i needs hello.c. Make hello.c first.
3. hello.c is "made" already. Nothing to do.
4. Now make hello.i i.e., run gcc -E hello.c -o hello.i.
5. Stop

Then you ran Make again (without any specific target)

1. hello.i exists already. Nothing to do.
2. Stop.

I suspect that you wanted to make "hello", i.e., your program.

Either:

1. Move "hello" at the top and make it your default target
2. Or run make hello