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chisel

Remove Bundle prefixes for nested bundles?

I have a bunch of Verilog IPs that for various reasons we don't want to (or can't easily) convert to Chisel, but I want to take advantage of some of the configurability with Chisel for now until we can transition some of the designs.

My goal is to be able to instantiate my IPs as BlackBoxes, then use Chisels Bundle connection features. I have researched and played around with the BlackBox/ExtModule classes, and this seems to be what I need. The only issue I'm running into right now is that I would like to be able to create sub-Bundles of signal groups. See the image for a simple example: enter image description here

And here is an example of what I want my BlackBox class to look like:

class BB1 extends BlackBox {
  val io = IO(new Bundle{
    val other_TOP = (new Bundle{
      val in0                                   = Input      (Bool())                                                
      val in1                                   = Input      (Bool())                                                
      val d0                                    = Input      (UInt(4.W))                                             
      val d1                                    = Input      (UInt(4.W))                                             
    })

    val apb = (new Bundle{
      val apb_clk                               = Input      (Bool())
      val apb_paddr                             = Input      (UInt(8.W))                                             
      val apb_penable                           = Input      (Bool())                                                
      val apb_psel                              = Input      (Bool())                                                
      val apb_pwrite                            = Input      (Bool())                                                
      val apb_rddata                            = Output     (UInt(32.W))                                            
      val apb_reset                             = Input      (Bool())                                                
      val apb_wrdata                            = Input      (UInt(32.W))                        
    })

    val other_BOTTOM = (new Bundle{
      val out0                                  = Input      (Bool())                                                
      val dout0                                 = Input      (UInt(18.W))                                            
    })
  })
}

This works as expected, however the issue I get is the sub-Bundle name is prefixed to the signal name. e.g. apb_clk has the name apb_apb_clk in the instantiation. I understand why this is happening, but is there anyway to disable this feature? I have tried some .suggestName, but it didn't seem to have any effect.

This issue on github (https://github.com/freechipsproject/chisel3/issues/612) seems to relate to the same issue, although the OP was asking for MultiIOModule. I saw where the last comment was a "Won't Fix". I'm wondering if additions have been made for this feature, or if there is any workaround outside of creating a wrapper. I'm actually looking to use Chisel to connect multiple BlackBoxes, so I'd prefer not to make wrappers just to connect these up.

Thank you for the help

Solution

  • Just to answer this. I ended up using Bundle names to "trick" the compiler to what I wanted the names and Bundle relationships to be (which basically turned out to be a wrapper). While it's not an entirely clean solution, I'll say that how Chisel/FIRRTL creates RTL in such a way that an additional wrapper is not that much extra work/hierarchy to allow BlackBox modules to be integrated easily.