Questasim - Is it possible to log and reload signals on new design?

Question

I am running a test (UVM) with lot of components. It is a Top-Level test, however I am debugging an internal module and I am only interested in the signals of the interfaces connected to that module. Since it is a TL it takes long time since I get to the point in time I am interested in. Those signals are product of other modules but I am not interested in those right now.

At the moment I am using Questa sim, so I was wondering if there is a way of storing the events from those signals so that I can rerun again only those. Hence my intention is to change the module, recompile and directly use the inputs on the new version without having to actually run the whole test and wait that long.

Answer 1

Inside a big chip company I used to work at, they call it "Save and Restore". Not sure what your EDA vendor calls it. You should be able to take a "Vector Change Dump" or "VCD" file of the signal snapshot at the end of the bootup simulation and convert that to a bunch of 0-time puts on the wires. You may have to force the wires for a few clocks and then release the force's.

In regards to your comment about interacting with UVM testing infrastructure, I'm not exactly sure on the behavior of multiple puts or forces on one node. I would guess that the last one wins. However, forces are very very very node specific. The reset force will win and be latched into design if your if it is down stream. If your design looks like this, then the force <path> 0 from the reset code will win, because it is downstream:

                +--------------------------------------------+
                |  TopDesign.sv  +------------------------+  |
                |                | SubBlock.sv            |  |
                |                |                        |  |
           1    | 1              |  0 +--------------+ 0  |  |
           ----->---------------->----> register Foo >--  |  |
           ^    |                |  ^ |              |    |  |
    UVM Driver  |                |  | +--------------+    |  |
                |                +--|---------------------+  |
                +-------------------|------------------------+
                                    |0
                                   Reset force

If your UVM infrastructure forces on an interface and then your reset initialization force is on a downstream node, which will synthesize to the same wire, then the downstream node force will win, because this will actually be flopped into the logic.

You still have to take care of initializing the UVM checkers or scoreboards into a post-reset state.