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cachingarmcpu-architecturearmv8

Armv8 address fields for cache?

I am reading, ARM Cortex-A Series Programmer’s Guide for ARMv8-A.

In 11.1.2 Cache tags and Physical Addresses, There was an example for cache address fields.

Example:

Cache is 4-way 32KB

Cache line = 16-words (64 Byte)

And the address fields stated in the document: Set(index) = 8 bits, Offset = 6 bits, Tag = 30 bits

From my understanding, 8 bits index will correspond to 256 cache lines in each way (which is illustrated correctly in the example). And offset is 6 bits (2^6 = 64) which is used to address bytes inside the line(64 bytes) correctly.

However the cache is 4 way which means that cache size is 4*256*64 = 64KB not 32KB.

Is my analysis correct or I am missing something ?

Solution

  • Someone asked the same question on arm community website: https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/8159/how-to-compute-a-cache-size

    Here is the reply on his question:

    " Got reply from ARM. It is a document error. It should be 2-way set-associative cache. 16KB * 2 = 32 KB "