Can we write to two signals from a port map statement?

Question

This is perhaps more of a hypothetical VHDL question as opposed to a real-life/case study question.

Say I have a component declaration as follows...

component my_comp is
    port (
    A : in std_logic;

    --...other input/outputs

    B : out std_logic_vector(9 downto 0)
);
end component my_comp;

And within the same entity containing my_comp i have the signals

signal my_comp_full_scale_output : std_logic_vector(9 downto 0);
signal my_comp_8_scale_output    : std_logic_vector(7 downto 0);

Is there a way which I can assign these two signals both the value of B in the port map statement of the component instantiation? Something like this maybe...

my_comp_isnt : my_comp
    port map (
    A => some_signal,

    -- other signal assignments

    B => my_comp_full_scale_output,
    B(9 downto 2) => my_comp_8_scale_output
);

Once again I stress that this is totally playing with VHDL's logic and I am not using this in any design!!! I do know that this can easily be done with an assignment of my_comp_full_scale_output to my_comp_8_scale_output outside of the component instantiation such as below and this is simply a sake of code for code's sake.

my_comp_isnt : my_comp
    port map (
    A => some_signal,

    -- other signal assignments

    B => my_comp_full_scale_output
);

my_comp_8_scale_output <= my_comp_full_scale_output(9 downto 2);

Answer 1

No.

1076-2008 - IEEE Standard VHDL Language Reference Manual states:

Each association element in an association list associates one actual designator with the corresponding interface element in the interface list of a subprogram declaration, component declaration, entity declaration, block statement, or package.

So you can only map it once.