so my issue is either out of my understanding of fpu mechanics, or there is a problem with implementation I am using.
Issue: When performing fused multiply-add instruction with source operand values as such, rs1 = 0xBF800000, rs2 = 0x80542353, rs3 = 0x80800000 the result is rd = 0x802BDCAD which is fine, but as it is subnormal(tiny) value I am pretty sure that fpu flag U(underflow) should be set. For some reason it is not. RISC-V documentation states that subnormal values handling conforms with ieee754-2008 on verifying tininess after rounding, which states that underflow will be signalled if result is smaller(but not 0) than smallest normal value(in that case 2^-126), and this result clearly is.
Am I missing something and flag is unnecessary or there may be issue with implementation ?
IEEE-754 does not say that, using detection of tininess after rounding, underflow will always be signaled if the result is smaller than the smallest normal but not zero. Although IEEE-754 2008 7.5 starts with this in its first sentence, its last paragraph says “In addition, under default exception handling for underflow, if the rounded result is inexact… the underflow flag shall be raised and the inexact (see 7.6) exception shall be raised. If the rounded result is exact, no flag is raised, and no inexact exception is signaled.…”
So, if traps are not enabled for the underflow exception (underflow exceptions will be handled in a default manner, providing the usual result without interrupting program execution), then, as long as a result is exact, no information has been lost due to the result being tiny, and the underflow flag will not be raised.