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How to connect ports to a Bus properly in VHDL?

i am currently fooling around with some VHDL Code to try out a view things. For my current approach i need to split up a bus into ports. Therefore it would be the prettiest solution to "hard connect" the bus with the ports in the entity declaration. Is this possible?

Or is the only solution to connect them in the architecture and "write" them into each other in there?

This is the snippet i am trying to implement accordingly. 

entity test is
  port (
    bus    : out std_ulogic_vector(3 downto 0);
    port3   : out std_ulogic;
    port2   : out std_ulogic;
    port1   : out std_ulogic;
    port0   : out std_ulogic;
  );
end test;

Thank you very much for your help.

Solution

  • The entity describes the external connectivity. The Architecture describes its internal behaviour. So "hardwiring" in the entity is not possible.

    In your example, you would need to connect the ports to the same connects as the "bus" output

    Note: bus is a reserved word in VHDL.