Let's say I have an atomic load-modify-store operation:
1: ldaxr x8, [x9]
orr x10, x8, #1
stlxr w11, x10, [x9]
cbnz w11, 1b
If I understand this correctly, when this code is executed on two cores (access to the same memory address), then thread A locks the resource with ldaxr. stlxr in thread B fails and operation is retried until thread A releases the lock.
But what happens if an interrupt occurs after ldaxr in main thread and interrupt handler tries to access the same memory address? Will it dead-lock or interrupt handler takes precedence and stlxr in main thread will fail when returned from the interrupt?
The stlxr in the main thread will fail.
ldaxr and stlxr are Load-link/Store-conditional instructions, they are lock-free, the user must be prepared to repeat the LL/SC.
Whenever an address is read using a Load Exclusive instruction, it is marked as being for an exclusive access. If an address marked as exclusive is written to using a Store Exclusive instruction, it clears the exclusive status. An attempt to write to an address not marked as exclusive using a Store Exclusive instruction will not succeed. This enables software to detect if the contents of that address have been changed since the last time it was read.