Multidimensional array partial assignment in VHDL

Question

I declared 2 types of array:

typeA is array(0 to 15) of std_logic_vector(15 downto 0);
typeB is array(0 to 7) of std_logic_vector(15 downto 0);

Then I instantiated 3 signals:

X1 : typeA;
X2, X3 : typeB;

I would like to assign the first 8 vectors of X1 to X2, the others to X2:

X2 <= X1(0 to 7);
X3 <= X1(8 to 15);

But I get an error because the right part of the assignment is not the same as the left one, but the dimensions are supposed to match. What is the correct way of doing it?

Answer 1

The issue is that TypeA and TypeB are different (although similar) types, so you cannot directly assign one to the other. Because they are similar (they are both arrays of the same subtype), you are allowed to cast from one type to the other.

X2 <= typeB(X1(0 to 7));

An easier fix for this might be just to declare the type as unconstrained, and constrain it at the declaration:

type slv16_array_t is array(natural range <>) of std_logic_vector(15 downto 0);

X1: slv16_array_t(0 to 15);
X2: slv16_array_t(0 to 7);

X2 <= X1(0 to 7); -- these are the same type already, so can be assigned to each other without a cast