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How to modify Vivado 2018.3 generated tcl script for version control

I am trying to modify a Vivado 2018.3 created tcl script for version control. As soon as I try to put all VHDL files in one directory (and modify the script accordingly), the script can't find all files when calling source build.tcl

I tried to follow version control instructions for older Vivadoversions like this one: https://github.com/tobiasrj20/Vivado-Version-Control-Example.

Unfortunately I couldn't find instructions for Vivado 2018.3, since the example script looks different to what I get from Vivado.

The structure of the Vivado Project.srcs folder looks as follows.

  • constr_1
    • imports
      • project_1 <--Here is the constraints file

  • sim_1

    • sources_1
      • bd
        • contains some stuff I don't use
      • imports
        • Downloads <-- contains a part of vhd files
        • new <-- contains another part of vhd files
      • new <-- contains other vhd files

My goal is to move all the vhd files to one folder, for example called "src". And to modify the tcl script accordingly.

I changed the parts in the script according to the tutorial given above. And replaced all absolute paths with relative paths. For example like this:

Original script

set files [list \
 [file normalize "${origin_dir}/fpga_top_v2.srcs/sources_1/new/clk_gen_25M.vhd" ]\

Modified:

set files [list \
 [file normalize "$
$origin_dir/src/clk_gen_25M.vhd" ]\

Then there is this part, where I am not sure if I need to change it

# Set 'sources_1' fileset file properties for local files
set file "new/clk_gen_25M.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj

Because the tcl console says the following during the source process:

# set file "new/clk_gen_25M.vhd"
WARNING: [Vivado 12-818] No files matched '*new/clk_gen_25M.vhd'
# set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
# set_property -name "file_type" -value "VHDL" -objects $file_obj
ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

Apologies, if this question has been asked before but I couldn't find any answers for this kind of question and especially for the Vivado 2018.3 version.

Solution

  • Here is how I got a working tcl script:

    Assuming I use a tcl script for the following folder structure:

    • src
      • constr <--contains the constraints file
      • sim <-- contains all simulation files
      • hdl <-- contains all files for syntheszis

    Make sure that

    set _xil_proj_name_ "<project name>"

    is named according to your wishes.

    Replace

    set origin_dir "."

    with

    set origin_dir [file dirname [info script]]

    And 

    create_project ${_xil_proj_name_} ./${_xil_proj_name_}

    with 

    create_project ${_xil_proj_name_} $origin_dir/${_xil_proj_name_}

    There might be a "-part xxx" statement that fits for the FPGA you want to synthesize your design for. This can be added to the replacement code above.

    For vhdl files that will be synthesized, search for the following line:

    # Set 'sources_1' fileset object

    The lines below should like this:

     [file normalize "${origin_dir}/src/hdl/<file name>.vhd"]\

    Futhermore, ach file needs a descriptive block like this, with a link to the directory where it is now. (This is where I failed in the initial question):

    set file "hdl/<file name>.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj

    The same goes for simulation and constraints files. Simulation files can be found at 

    # Set 'sim_1' fileset object

    Make sure that all the files are pointing to the correct src/xxx/.vhd directory.