VHDL: formal port 'portName' has no actual or default value

Question

I receive a compilation error on VHDL test bench instantiating VHDL module PWM: "formal port 'Duty_Cycle' has no actual or default value". The error is seen when standing on "dev_to_test: PWM" line of code. In instantiated PWM module the Duty_Cycle stg_logic_vector is casted to unsigned and then is assigned to integer but don't think this may influence the port instantiation. I tried to pass the "00001111" vector value in the port map, which results in the same error. Please, help determine what the error is.

architecture test of test_pwm is
component PWM
    Generic (
        BIT_DEPTH   : integer;
        INPUT_CLK   : integer; -- 50MHz
        FREQ        : integer); -- 50Hz
    Port (
        Pwm_Out     : out std_logic;
        Duty_Cycle  : in std_logic_vector(BIT_DEPTH - 1 downto 0);
        Clk         : in std_logic;
        Enable      : in std_logic);
end component;

constant BIT_DEPTH  : integer := 8;
constant INPUT_CLK  : integer := 125000000; -- 50MHz
constant FREQ       : integer := 50; -- 50Hz

signal Enable      : std_logic := '0';
signal Duty_Cycle  : std_logic_vector(BIT_DEPTH - 1 downto 0) := "00001111";
signal Clk         : std_logic := '1';
signal Pwm_Out     : std_logic;   


begin
    dev_to_test: PWM
        generic map(BIT_DEPTH,INPUT_CLK,FREQ);
        port map(Pwm_Out,Duty_Cycle,Clk,Enable);

Answer 1

IEEE Std 1076-2008

11.7 Component instantiation statements

component_instantiation_statement ::=
    instantiation_label :
        instantiated_unit
            [ generic_map_aspect ]
            [ port_map_aspect ] ; 

and

generic_map_aspect ::=     
   generic map (generic_association_list ) 

You have a semicolon too much at the end of generic map(BIT_DEPTH,INPUT_CLK,FREQ);, for this reason, it is not seeing the mapping of the ports and giving you the error. To solve the error just delete that semicolon:

dev_to_test: PWM
        generic map(BIT_DEPTH,INPUT_CLK,FREQ)
        port map(Pwm_Out,Duty_Cycle,Clk,Enable);

PS: to reduce the risk of design errors, it is good practice to use named association in port and generic mapping instead of positional.