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delayareaenergyyosys

Characterization using YOSYS

Is there any way to obtain the Area, Energy Consumption or time delay of a mapped circuit using YOSYS?

This is my synthesis script:

read_verilog UBBKA_15_0_15_0.v
hierarchy -top UBBKA_15_0_15_0
prep; flatten; synth
clean -purge

dfflibmap -liberty NanGate15nm.lib
abc -liberty NanGate15nm.lib
clean -purge

write_verilog -noattr -noexpr netlits.v
Solution

  • You can use stat or stat -lib (with a liberty file) for area/gate usage information.

    When given a delay target with -D, abc will print some delay information about the mapping (at a minimum, whether it was able to meet that target).

    I am not aware of a way to do power analysis with Yosys at present.