Why do incomplete if statements create latches during synthesis in VHDL?

Question

Why is it when we try to synthesize incomplete if statements in VHDL the synthesizer uses latches instead of flip-flops?

An explanation from a digital/circuit standpoint would be greatly appreciated.

Answer 1

Short answer: because the behaviour of a latch matches that of an incomplete IF. A register does not.

if (A)
   B = C;

If the condition A is true and C changes, the output B follows the input immediately. If A is false B keeps it value. This behavior of the IF statement corresponds with the behavior of a latch. Thus a latch is what is generated.

You can not generate this behaviour with a register.