A problem with the output of a 4to1 mux made using 2to1 mux's in Modelsim

Question

After a successful compilation and simulation using Modelsim of the code beneath, which is just a simple 4to1 mux built using two 2to1 mux's, I ran a waveform test to see what it would look like, the output was continuously in the U state regardless of the values the inputs, here is the code along with the results:

a. The code for the 2to1 mux:

entity mux2_1 is
port( a,b:in std_logic_vector(2 downto 0);
s:in std_logic;
e:out std_logic_vector(2 downto 0));
end mux2_1;


architecture wx of mux2_1 is

begin

process

begin
if(s='0') then
e<=a;
else
e<=b;
end if;
wait;

end process;
end wx;

b. The code for the 4to1 mux:

entity mux4_1 is

port( a,b,c,d:in std_logic_vector(2 downto 0);
       s1,s0:in std_logic;
       e :out std_logic_vector (2 downto 0));

end mux4_1;


architecture nj of mux4_1 is

signal t1,t2:std_logic_vector (2 downto 0);


begin

k1: entity work.mux2_1 port map (a,b,s0,t1);
k2: entity work.mux2_1 port map (c,d,s0,t2);
k3: entity work.mux2_1 port map (t1,t2,s1,e);

end nj;

Here's the console report just after simulating:

And finally, the waveforms, with the inconsistent output:

Answer 1

I believe the error is due to the 'wait' statement in your 2:1 mux. Please remove it.

Here's a side note: use the wait statements as much as possible in the testbench only. As waits are non-synthesizable, you will come across a few errors.

Thank you