How to make this VHDL 'for' loop work with no error on modelsim?

Question

I have a 'for' loop in my VHDL design that gives an error on modelsim : "Illegal concurrent statement".

My VHDL architecture is a few hundreds lines long so I will just show what gives an error :

for k in 0 to 19 loop
    DATA_SERDES(k)  <= DATA_SERDES_inv(19-k);
end loop;

It works when I replace the loop by :

DATA_SERDES(0)      <= DATA_SERDES_inv(19);
DATA_SERDES(1)      <= DATA_SERDES_inv(18);
DATA_SERDES(2)      <= DATA_SERDES_inv(17);
DATA_SERDES(3)      <= DATA_SERDES_inv(16);
DATA_SERDES(4)      <= DATA_SERDES_inv(15);
DATA_SERDES(5)      <= DATA_SERDES_inv(14);
DATA_SERDES(6)      <= DATA_SERDES_inv(13);
DATA_SERDES(7)      <= DATA_SERDES_inv(12);
DATA_SERDES(8)      <= DATA_SERDES_inv(11);
DATA_SERDES(9)      <= DATA_SERDES_inv(10);
DATA_SERDES(10)     <= DATA_SERDES_inv(9);
DATA_SERDES(11)     <= DATA_SERDES_inv(8);
DATA_SERDES(12)     <= DATA_SERDES_inv(7);
DATA_SERDES(13)     <= DATA_SERDES_inv(6);
DATA_SERDES(14)     <= DATA_SERDES_inv(5);
DATA_SERDES(15)     <= DATA_SERDES_inv(4);
DATA_SERDES(16)     <= DATA_SERDES_inv(3);
DATA_SERDES(17)     <= DATA_SERDES_inv(2);
DATA_SERDES(18)     <= DATA_SERDES_inv(1);
DATA_SERDES(19)     <= DATA_SERDES_inv(0);

For me both declarations are equivalent, but modelsim sees an error. I don't have any other "k" variable or any other loop in the architecture. I am using VHDL 93 and compiling with modelsim 10.4c

Any idea ?

Thanks,

SLP

Answer 1

The for loop can be used only inside processes, functions or procedures. Maybe what you are looking for is the "generate" statement:

generate_label: for k in 0 to 19 generate
    DATA_SERDES(k)  <= DATA_SERDES_inv(19-k);
end generate;