Can we overwrite a variable in a loop over VHL?

Question

I have to implement a loop that updates a variable (or signal) in a loop over VHDL. In other terms, I have to implement this pseudo-code

res = 1
while condition:
   res = res * val    #for example, but it could be another operation
return res

I know that it's not possible to update the value of a signal in VHDL so I don't know how to proceed.

I have tried for example creating an array of nb_iterations elements where I put the updated value in the corresponding case of the array. But my number of iterations can be a really big number sometimes, so it's not efficient to keep such a big array in memory.

Is there any way to update or overwrite a signal over VHDL that makes it possible to implement such a loop?

Answer 1

Try the pseudo code, where resVar is a variable and ResSig is a signal.

      resVar = 1    
      while condition:    
        resVar = resVar * val     
      end loop    
      ResSig = resVar    

WRT signal update, it is correct that signals do not update until the process suspends - which for RTL code is generally after it has exited, but for testbench code the process also suspends at every wait statement