I am very new to VHDL and as a part of a university project, I am trying to create a statemachine with four states. I wrote some VHDL Code and a testbench, but I could not yet confirm if the statemachine works at all, but I will verify this after I solved the current problem:
Part of the statemachine is an unsigned counter which should determine, whether to fetch data to a highbyte or a low byte. In my testbench, I just want to confirm if this counter works at all. Right now, after being initialized with 0, when the counting process starts the first time, I receive an undefined Value as the counter value.
At first, I tried to implement the counter as a std_logic_vector, but I understood, why this could not work (without cast). So I switched to unsigned and expected the counter to work. By commenting single processes out I found out, that the counting process produces problems with the process "change status" and "change_current_state". But I just can't figure out why these processes interfere with each other. "change_current_state" never reaches the "RESET" if - statement in my testbench, so it can't assign a value to the counter. Also, the process "change_status" never reaches the elsif - statement with the state being "prepareData" This is the only statement in which a value is assigned to the counter.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity readFromADC is
Port
(
CLK_IN : in std_logic;
RESET_IN_N : in std_logic;
BUSY_IN : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
ACK_ERROR_IN : in std_logic;
ENABLE_I2C : out std_logic;
ADDR_I2C : out std_logic_vector(6 downto 0);
RW_I2C : out std_logic;
DATA_WR_I2C : out std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
SHIFT_OUT_RDY : out std_logic;
SHOWSTATE : out std_logic_vector (1 downto 0); -- debugging
BYTECOUNTER: out unsigned (1 downto 0)
);
end readFromADC;
architecture readFromADC_arch of readFromADC is
constant const_data_wr : std_logic_vector(7 downto 0) := "00000000";
constant const_rw_I2C : std_logic := '1';
constant const_addr_I2C : std_logic_vector(6 downto 0) := "0101000";
constant const_da2_control : std_logic_vector (3 downto 0) := "0000";
type states is
(
idle,
read,
prepareData,
shiftOut
);
signal sign_clk : std_logic;
signal sign_HighByte : std_logic_vector(7 downto 0);
signal sign_LowByte : std_logic_vector(7 downto 0);
signal current_state : states;
signal next_state : states;
signal sign_data_out : std_logic_vector(15 downto 0);
signal sign_ena_i2c : std_logic := '0';
signal sign_count_bytes_uns : unsigned (1 downto 0) := "00";
signal prepare_data_rdy : std_logic := '0';
signal sign_shift_out_rdy : std_logic := '0';
signal debug_states : std_logic_vector (1 downto 0);
begin
--Zuweisungen
sign_clk <= CLK_IN;
ENABLE_I2C <= sign_ena_i2c;
ADDR_I2C <= const_addr_I2C;
RW_I2C <= const_rw_I2C;
DATA_WR_I2C <= const_data_wr;
DATA_OUT <= sign_data_out;
SHIFT_OUT_RDY <= sign_shift_out_rdy;
SHOWSTATE <= debug_states;
BYTECOUNTER <= sign_count_bytes_uns;
--nächsten Status zuweisen
change_current_state : process (sign_clk, RESET_IN_N)
begin
if rising_edge(sign_clk) then
if (RESET_IN_N = '0') then
current_state <= idle;
sign_shift_out_rdy <= '0';
sign_data_out <= (others => '0');
sign_count_bytes_uns <= "00";
else
current_state <= next_state;
end if;
end if;
end process change_current_state;
--Status ändern
change_status : process (current_state)
begin
if current_state = idle then
debug_states <= "00";
sign_shift_out_rdy <= '0';
prepare_data_rdy <= '0';
sign_ena_i2c <= '1';
elsif current_state = read then
debug_states <= "01";
-- sign_count_bytes <= sign_count_bytes + 1;
sign_shift_out_rdy <= '0';
elsif current_state = prepareData then
debug_states <= "10";
sign_ena_i2c <= '0';
-- sign_count_bytes <= "00";
elsif current_state = shiftOut then
sign_count_bytes_uns <= "00";
debug_states <= "11";
sign_shift_out_rdy <= '1';
end if;
end process change_status;
acquireData : process (sign_count_bytes_uns, current_state)
begin
if current_state = read then
if (sign_count_bytes_uns = 1) then
sign_HighByte <= DATA_IN;
elsif (sign_count_bytes_uns = 2) then
sign_LowByte <= DATA_IN;
end if;
end if;
end process acquireData;
gatherData : process (current_state)
begin
if current_state = prepareData then
sign_data_out <= const_da2_control & sign_HighByte(3 downto 0) & sign_LowByte;
prepare_data_rdy <= '1';
end if;
end process gatherData;
--Dekodiere den nächsten Status
next_state_decode: process (current_state, BUSY_IN, ACK_ERROR_IN, sign_count_bytes_uns, prepare_data_rdy, sign_shift_out_rdy)
begin
next_state <= current_state; --Default: behalte den aktuellen Status
case (current_state) is
when Idle =>
if (BUSY_IN = '0') AND (ACK_ERROR_IN = '0') then
next_state <= read;
end if;
when read =>
if sign_count_bytes_uns >= 2 then
-- if sign_count_bytes = "11" then
next_state <= prepareData;
end if;
when prepareData =>
if prepare_data_rdy = '1' then
next_state <= shiftOut;
end if;
when shiftOut =>
if sign_shift_out_rdy = '1' then
next_state <= Idle;
end if;
end case;
end process next_state_decode;
countBusy : process (BUSY_IN)
begin
if falling_edge(BUSY_IN) then
sign_count_bytes_uns <= sign_count_bytes_uns + 1;
-- if (sign_count_bytes_uns <= 2) then
-- sign_count_bytes <= std_logic_vector (sign_count_bytes_uns);
if (sign_count_bytes_uns > 2) then
sign_count_bytes_uns <= "00";
end if;
end if;
end process countBusy;
Testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sim_read_adc is
-- Port ( );
end sim_read_adc;
architecture sim_read_adc_arch of sim_read_adc is
component readFromADC is
Port
(
CLK_IN : in std_logic;
RESET_IN_N : in std_logic;
BUSY_IN : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
ACK_ERROR_IN : in std_logic;
ENABLE_I2C : out std_logic;
ADDR_I2C : out std_logic_vector(6 downto 0);
RW_I2C : out std_logic;
DATA_WR_I2C : out std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
SHIFT_OUT_RDY : out std_logic;
SHOWSTATE : out std_logic_vector (1 downto 0);
BYTECOUNTER: out unsigned (1 downto 0)
);
end component readFromADC;
signal sim_CLK_IN : std_logic;
signal sim_RESET_IN_N : std_logic := '1';
signal sim_BUSY_IN : std_logic := '1';
signal sim_DATA_IN : std_logic_vector(7 downto 0) := "10101010";
signal sim_ACK_ERROR_IN : std_logic := '0';
signal sim_ENABLE_I2C : std_logic;
signal sim_ADDR_I2C : std_logic_vector(6 downto 0);
signal sim_RW_I2C : std_logic;
signal sim_DATA_WR_I2C : std_logic_vector(7 downto 0);
signal sim_DATA_OUT : std_logic_vector(15 downto 0);
signal sim_SHIFT_OUT_RDY : std_logic;
signal sim_SHOWSTATE : std_logic_vector (1 downto 0);
signal sim_BYTECOUNTER : unsigned (1 downto 0);
begin
dut : readFromADC
port map
(
CLK_IN => sim_CLK_IN,
RESET_IN_N => sim_RESET_IN_N,
BUSY_IN => sim_BUSY_IN,
DATA_IN => sim_DATA_IN,
ACK_ERROR_IN => sim_ACK_ERROR_IN,
ENABLE_I2C => sim_ENABLE_I2C,
ADDR_I2C => sim_ADDR_I2C,
RW_I2C => sim_RW_I2C,
DATA_WR_I2C => sim_DATA_WR_I2C,
DATA_OUT => sim_DATA_OUT,
SHIFT_OUT_RDY => sim_SHIFT_OUT_RDY,
SHOWSTATE => sim_SHOWSTATE,
BYTECOUNTER => sim_BYTECOUNTER
);
clk_gen : process
begin
sim_CLK_IN <= '0';
wait for 0.5us;
sim_CLK_IN <= '1';
wait for 0.5us;
end process clk_gen;
generate_busy : process
begin
wait for 5us;
sim_BUSY_IN <= '0';
wait for 1us;
sim_BUSY_IN <= '1';
end process generate_busy;
end sim_read_adc_arch;
Simulation(no process is commented out): Simulation(no process is commented out)
*EDIT: The updated VHDL - Code (testbench didn't have to be changed):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity readFromADC is
Port
(
CLK_IN : in std_logic;
RESET_IN_N : in std_logic;
BUSY_IN : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
ACK_ERROR_IN : in std_logic;
ENABLE_I2C : out std_logic;
ADDR_I2C : out std_logic_vector(6 downto 0);
RW_I2C : out std_logic;
DATA_WR_I2C : out std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
SHIFT_OUT_RDY : out std_logic;
SHOWSTATE : out std_logic_vector (1 downto 0); -- debugging
BYTECOUNTER: out unsigned (1 downto 0)
);
end readFromADC;
architecture readFromADC_arch of readFromADC is
constant const_data_wr : std_logic_vector(7 downto 0) := "00000000";
constant const_rw_I2C : std_logic := '1';
constant const_addr_I2C : std_logic_vector(6 downto 0) := "0101000";
constant const_da2_control : std_logic_vector (3 downto 0) := "0000";
type states is
(
idle,
read,
prepareData,
shiftOut
);
signal sign_clk : std_logic;
signal sign_HighByte : std_logic_vector(7 downto 0);
signal sign_LowByte : std_logic_vector(7 downto 0);
signal current_state : states;
signal next_state : states;
signal sign_data_out : std_logic_vector(15 downto 0);
signal sign_ena_i2c : std_logic := '0';
signal sign_count_bytes_uns : unsigned (1 downto 0) := "00";
signal prepare_data_rdy : std_logic := '0';
signal sign_shift_out_rdy : std_logic := '0';
signal debug_states : std_logic_vector (1 downto 0);
begin
--Zuweisungen
sign_clk <= CLK_IN;
ENABLE_I2C <= sign_ena_i2c;
ADDR_I2C <= const_addr_I2C;
RW_I2C <= const_rw_I2C;
DATA_WR_I2C <= const_data_wr;
DATA_OUT <= sign_data_out;
SHIFT_OUT_RDY <= sign_shift_out_rdy;
SHOWSTATE <= debug_states;
BYTECOUNTER <= sign_count_bytes_uns;
--nächsten Status zuweisen
change_current_state : process (sign_clk, RESET_IN_N)
begin
if rising_edge(sign_clk) then
-- if (RESET_IN_N = '0') then
-- current_state <= idle;
-- sign_shift_out_rdy <= '0';
-- sign_data_out <= (others => '0');
-- sign_count_bytes_uns <= "00";
-- else
current_state <= next_state;
-- end if;
end if;
end process change_current_state;
--Status ändern
change_status : process (current_state)
begin
if current_state = idle then
debug_states <= "00";
sign_shift_out_rdy <= '0';
prepare_data_rdy <= '0';
sign_ena_i2c <= '1';
elsif current_state = read then
debug_states <= "01";
sign_shift_out_rdy <= '0';
elsif current_state = prepareData then
debug_states <= "10";
sign_ena_i2c <= '0';
elsif current_state = shiftOut then
debug_states <= "11";
sign_shift_out_rdy <= '1';
end if;
end process change_status;
acquireData : process (sign_count_bytes_uns, current_state)
begin
if current_state = read then
if (sign_count_bytes_uns = 1) then
sign_HighByte <= DATA_IN;
elsif (sign_count_bytes_uns = 2) then
sign_LowByte <= DATA_IN;
end if;
end if;
end process acquireData;
gatherData : process (current_state)
begin
if current_state = prepareData then
sign_data_out <= const_da2_control & sign_HighByte(3 downto 0) & sign_LowByte;
prepare_data_rdy <= '1';
end if;
end process gatherData;
--Dekodiere den nächsten Status
next_state_decode: process (current_state, BUSY_IN, ACK_ERROR_IN, sign_count_bytes_uns, prepare_data_rdy, sign_shift_out_rdy)
begin
next_state <= current_state; --Default: behalte den aktuellen Status
case (current_state) is
when Idle =>
if (BUSY_IN = '0') AND (ACK_ERROR_IN = '0') then
next_state <= read;
end if;
when read =>
if sign_count_bytes_uns >= 2 then
-- if sign_count_bytes = "11" then
next_state <= prepareData;
end if;
when prepareData =>
if prepare_data_rdy = '1' then
next_state <= shiftOut;
end if;
when shiftOut =>
if sign_shift_out_rdy = '1' then
next_state <= Idle;
end if;
end case;
end process next_state_decode;
countBusy : process (BUSY_IN, RESET_IN_N)
begin
if falling_edge (RESET_IN_N) then
sign_count_bytes_uns <= "00";
elsif falling_edge(BUSY_IN) then
sign_count_bytes_uns <= sign_count_bytes_uns + 1;
if (sign_count_bytes_uns > 2) then
sign_count_bytes_uns <= "00";
end if;
end if;
end process countBusy;
end readFromADC_arch;
First, get some 'X' in simulation usually means that a signal is assigned to 2 (or more) value at the same time. That often implies that you assign this signal in several concurrent process.
In VHDL, it's better to avoid assigning a signal in 2 different process (Note that a line outside of any process is a process).
In your code, the signal sign_count_bytes_uns is affected in 3 process. I think you should modify at least 2 of them (by merging them).
But the real reason of your 'X' is a little bit more tricky, in this process :
change_status : process (current_state)
begin
if current_state = idle then
debug_states <= "00";
sign_shift_out_rdy <= '0';
prepare_data_rdy <= '0';
sign_ena_i2c <= '1';
elsif current_state = read then
debug_states <= "01";
sign_shift_out_rdy <= '0';
elsif current_state = prepareData then
debug_states <= "10";
sign_ena_i2c <= '0';
elsif current_state = shiftOut then
sign_count_bytes_uns <= "00";
debug_states <= "11";
sign_shift_out_rdy <= '1';
end if;
end process change_status;
You assign sign_count_bytes_uns in only 1 case and I assume you are not in this case in the simulation screenshot you gave us but sign_count_bytes_uns is still to "XX".
The reason is the following : When you assign a signal in a process but not in all cases, each time you are not in a case where the signal is affected, this signal will take his previous value (memory). In synthesis, a latch will be infered. So your process change_status maintains sign_count_bytes_uns to "00" when countBusy tries to change it that's why you get some "XX".