The Verilog standard clearly states that there is no functional difference between a wire and a tri. The differentiation is that of convention. A wire net is used for nets driven by a single gate or continuous assignment while the tri net can be used where multiple drivers drive a net [$4.6.1]. Given this fact, I have these questions:
Thanks,
The wire
and tri
keywords were designed to document the user's intent that a signal could have the tristate Z value at some point in time. However Verilog never implemented any kind of check to enforce this usage. So now they are simply keyword synonyms (same as reg
and logic
being synonyms with no functional difference).
Wired-or or Wired-and logic get created by certain transistor technologies. (See open-collector circuits)