Hello I have a homework question I stuck on in computer structure class. I have a pipeline mips processor with forwarding and a code and I need to calculate the processor CPI. I know that I will get a stall after lw if I calculate something and after branch there will be some kind of stall to, also I calculated the frequency of each instruction.
How am I supposed to calculate the CPI? I know how to do it for multicycle but not how for pipeline.
would greatly appreciate any help you can give!
In a pipeline context, CPU is potentially able to read and start execution of an instruction at every cycle. So as CPI is concerned by execution throughput, without any data or control hazard creating a stall, we would consider that every instruction takes a cycle.
This is obviously wrong, as an instruction requires several cycles to complete, but a program with N>>1 instructions will take N cycles and we can consider that cycles per instruction is 1.
Now, what happens when we have a stall due to the latency of memory accesses, branch delay or whatever? Because of this stall, we will no longer have 1 instruction per cycle. During the stall the pipeline will be frozen or an improper instruction is fetched and the gross result is that a cycle is lost for the processor.
For this reason, we consider that an instruction that creates a 1 cycle stall last 2 cycles for what concerns CPI computation. Similarly, if there is a two cycles stall, we consider that instruction is 3 cycles and so on.
Assume that 50% of ld instructions create a stall, a hazard-less ld will have a a 1 cycle "duration" and if there is a stall, "duration" is 2 cycles, so we have on the average 1.5 cycles for a ld.
Assume also that branches are 2 cycles because of the branch delay.
If other instructions are 1 cycles, 20% of instructions are ld and another 20% are branches, we have
CPI = 0.20*1.5 + 0.20*2 + 0.6*1=1.3 cycle per instruction.