How to use System-Verilog Assertions on modules within top level DUT

Question

I'm trying to write a memory scheduling testbench and to verify that I am accessing the correct addresses and writing the correct values at the right time I want to compare what is going on with the signals inside my top module with my schedule that I developed.

I've tried looking up "dot notation" and using my simulator (ModelSim) to access the signal (which I can do on the waveform fine) but I want to be able to use SVAs to check I have the correct values.

module top(input d, output q)

    //wires
    wire sub1_output

    // Instantiate submodule
    sub_module1 sub1(.sub1_output(sub1_output));

    always begin
        // logic
    end
endmodule

module tb_top();

    reg d;
    wire q;

    DUT top(.*);

    initial begin
        // This is where I want to access something within my DUT
        assert(DUT.sub1_output == 1'b1)
    end
endmodule

When I try this my code compiles and runs, but if I write the assertion such that it should fail and stop my code, nothing happens.

Answer 1

DUT.sub1_output

Is the correct format to use assertions on signals within top level instantiations.