In VHDL, Can I use signal'event if signal is not a clock?

Question

I am trying to clean up my VHDL code. I have a signal that is NOT a clk.

Can I write an event change monitor like the following and how do I get it to compile so it can be synthesized? (see code) I have tried several permutations but I cannot get it to compile. Will signal'event compile if signal is not a CLK and if so, how is it done? I see on the web and other literature that it can be done but all examples I see show CLK'event.

signal cntr: unsigned(15 downto 0) := (others => '0');

...
process(CLK):
begin

IF rising_edge(CLK) THEN
    if (cntr'event) then
        do something;
    end if;
or...
    if(cntr(0)'event) then
        do something;
    end if;
END IF;
end process;

I get the following and others : can't synthesize condition that contains an isolated 'EVENT predefined attribute

Answer 1

rising_edge(CLK) is already an event, making your design synchronous, which is good. As said in comments, only clock signals should use that.
Looking at another even at that time doesn't make sense in synchronous designs, as the 2 signals won't change exactly at the same time, creating a race condition. Or actually a clock within a clock, and the synthesis error...
It may work in simulation, but don't rely on that fact.

The normal way to program in HDL languages is to save the previous value of the signal, on the same clock (for example cntr_d <= cntr) and to compare with that previous value. That allows to find if the signal went up (previously at 0, currently at 1), went down, changed (is different)...
And that method is perfectly fine for synthesis!