verilogsystem-verilogmodelsimquestasim
How to specify height of waveform in Modelsim/Questasim?
I'm using QuestaSim 70.7b; And I can not change the height of waveform signal.. I've tried many options, like this:
add wave -radix hex -format analog-step -scale 100 -height 100 -color gold /bin_top_tb/clk
But nothing happen, just height of the name signal is changed, like shown below
*thanks to dave_59, to change the height you should go to Tools -> Edit Preferences and change WaveFont and then footerFont exactly at such sequence, then click apply and ok.
Solution
There's no way to change the height of individual digital signal. You use the main preferences to select a larger Wave Window text font, and the size of the waveform gets scaled to match the wave label.
- T flip-flop using dataflow model
- Use if-generate structure to define two variations of a function, and call that function in the same tb
- SystemVerilog inheritance, aggregated classes and parent function call
- Verilog module instance named after different module type
- String triple quotes not getting accepted by simulators
- Verilog always @(posedge clk) dosent work
- Testbench for writing to the file in Verilog
- SystemVerilog not reading data correctly
- How can I schedule multiple inputs into an instantiated SystemVerilog module?
- Icarus Verilog Syntax error "I give up" for NAND gate
- How to specify AUTO_TEMPLATE wild card for inputs and outputs separately?
- localparam for case values with don't cares. Is 1'b? legal?
- Verilog how does assign statement work with a conditional operator?
- SystemVerilog parameter override unsigned
- Icarus verilog dump memory array ($dumpvars)
- Assign a SV port
- How do I install GTKWave on Windows?
- Missing data while shuffling
- Register increments twice within a non blocking always
- Can Verilog functions access variables declared outside the function block?
- How can I calculate a generate loop control value from a module parameter?
- Why is "Set as Top-Level Entity" grayed out in quartus?
- How to fix [Common 17-1293] error in Xilinx Vivado?
- How to initialize contents of inferred Block RAM (BRAM) in Verilog
- 'Illegal output or inout port' error when trying to simulate counter
- Assignment to two different wires with a bit and its complement yields the same value
- How to convert Signed Binary to Integer in Verilog?
- Rounding down the absolute value of signed fixed point numbers in Verilog
- Formal verification of state machine with SymbiYosys not giving expected results
- Matrix Multiplication Testbench Yields Inconsistent Results