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vhdl

How to split the 8 bit input into two 4 bit data

I'm writing a code for QPSK modulation in VHDL. I need to split the 8 bit input data into odd and even bits and each bit is replicated How can i do it.

for example if my input is 11001001 then odd and even bits are odd= 1010 even =1001 my output should be like odd= 11001100 and even is 11000011

Solution

  • Use the concatenation operator '&':

    dbl_odds  <=  v(7) & v(7) & v(5) & v(5) & v(3) & v(3) & v(1) & v(1);
dbl_evens <=  v(6) & v(6) & v(4) & v(4) & v(2) & v(2) & v(0) & v(0);