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system-verilogsystem-verilog-assertions

SystemVerilog assertion for primitive

is there a way to add an assertion for a SystemVerilog primitive or only in the module (cell) wrapping the primitive ? simply adding an assertion does not compile

   primitive mux (q, d0, d1, s);
   output q;
   input s, d0, d1;

   table
   // d0  d1  s   : q 
      0   ?   0   : 0 ;
      1   ?   0   : 1 ;
      ?   0   1   : 0 ;
      ?   1   1   : 1 ;
      0   0   x   : 0 ;
      1   1   x   : 1 ;
   endtable
   //assert(s != x) else $error("s has value x"); - add this assertion
endprimitive
Solution

  • The only construct allowed inside a user defined primitive (UDP) is the table. You'll need to wrap the UDP in a module to add anything else.