assign data(i) into std_logic_vector(0 downto 0) in vhdl

Question

I have the following problem:

My code has this constant value

constant source_vector : std_logic_vector(7 downto 0) := "1011000";

This value needs to be fed into a signal of type std_logic_vector, bit by bit. The problem is that the destination vector has a size defined in a constant. For the test, I am using size 1.

constant k : integer := 1;
dest_vector : in std_logic_vector(k-1 downto 0);

When I try to assign the first bit:

dest_vector <= std_logic_vector(to_unsigned(source_vector(0), k));

I got this error: ERROR: [VRFC 10-925] indexed name is not a natural

I have tried several things, but no luck. Perhaps I am missing something... Any advice here?

Answer 1

Answer from user1155120 Jul 16 '17 at 19:47

Use dest_vector <= source_vector(0 downto 0); which uses a slice name or dest_vector(0) <= source_vector(0); which uses indexed names for both target and right hand side. There's also dest_vector <= "" & source_vector(0); which derives the type of the concatenation result from context while concatenating a null array to a value of the element type. See IEEE Std 1076-2008 8.4 Indexed names, 8.5 Slice names, 9.2.5 Adding operators ("&") and 12.5 The context of overload resolution (which "&").