I have the following problem:
I have an adder whose output has 5 bits. I want to send this output to an 8-bit register.
I've declared the register input signal as tot_sig, and the adder output as add_out. Both the register and the adder are declared as separate components in my entity.
In the adder port map, I've tried to write the following:
add_out => tot_sig(4 downto 0)
But that won't work (ISE tells me that tot_sig and add_out have different sizes).
So I tought of declaring 2 signals, which would be the same thing, but in different sizes. I would first declare a signal called intermediary, which would be an 4-bit bus. Then, I would be adding the intermediary to an (initially set as "00000000") byte (total_sig). Then the total_sig byte would be connected at the input of the register.
I am worried that this may generate a latch. Can it? I tried thinking of simpler solutions but couldn't arrive to any. Any solution that could work without the necessity of declaring another signal would be nicer.
Thank you for your help and time.
I am using Xilix ISE Design Suite version 14.6.
The simple solution is to define an 8-bit vector an concatenate 3 zeros when assigning a 5-bit vector to it:
signal len5 : std_logic_vector (4 down to 0);
signal len8 : std_logic_vector (7 down to 0);
len8 <= "000" & len5;
-- Now you can pass len8 into an 8-bit port.
You do not get a latch. Latches only appear when you use a condition outside a clocked process and you have unresolved branches.
e.g. an if with no else or a case with not all possibilities covered.