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verilogsystem-verilogmodelsim

Priority case with for loop inside always_comb Procedural block gives error?

I am trying to build a static priority encoder, for example, 0011101010------>0010000000

Basically the index with highest value should be one and other indices must be zero.

I have tried the following code with modelsim and it gives error saying:

** Error: near "for": syntax error, unexpected for

** Error: syntax error, unexpected ')', expecting ';'

//code*******************************************

integer i;

always_comb begin

   priority case (1'b1)

      for ( i=0; i<16 ; i=i+1 ) 

         begin

           in[15-i] : out= 16'd2**(15-i);

         end

   endcase

end
Solution

  • There is no such syntax for generating case items in a for loop. You just need the for loop

    always_comb begin
      out  = 0;
      for (int i=15; i>=0 ; i-- ) 
           if (in[i]) begin
               out[i]= 1'b1;
               break;
           end
      end