How to perform bit extension in system verilog?

Question

I want to replicate one bit for specific times using replication opreator {} but I get only the first bit as I want and others are zeros whether the bit is zero or one.

module(logic output [7:0] a);
assign a={8{1}};
endmodule

I get a equals 00000001 Not 11111111

Answer 1

In Verilog an unbased literal (eg 1) is (a) decimal, (b) signed and (c) 32-bits. Because of (c),

{8{1}}

is the same as

{8{32'sb00000000000000000000000000000001}}

which is a 256-bit number, which then gets truncated to 8-bits when it gets assigned to a. This is why you get a equal to 8'b00000001.

You need

{8{1'b1}}