library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity keygeneration is
Port ( key : in STD_LOGIC_VECTOR (127 downto 0);
rc : in STD_LOGIC_VECTOR (3 downto 0);
keyout : out STD_LOGIC_VECTOR (127 downto 0));
end keygeneration;
architecture Behavioral of keygeneration is
component sbox is
port(a: in std_logic_vector(7 downto 0);
y: out std_logic_vector(7 downto 0));
end component;
component RCON is
Port ( rc : in STD_LOGIC_VECTOR (3 downto 0);
rout : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal w0,w1,w2,w3,tem: STD_LOGIC_VECTOR (31 downto 0);
signal rout1: STD_LOGIC_VECTOR (31 downto 0);
begin
-- 52nd line below
w0<=key[127 downto 96];
w1<=key[95 downto 64];
w2<=key[63 downto 32];
w3<=key[31 downto 0];
t1: sbox port map(w3[23 downto 16],tem[31 downto 0]);
t2: sbox port map(w3[15 downto 8],tem[23 downto 16]);
t3: sbox port map(w3[7 downto 0],tem[15 downto 8]);
t4: sbox port map(w3[31 downto 24],tem[7 downto 0]);
r1: RCON port map(rc[3 downto 0],rout1[31 downto 0]);
keyout[127 downto 96]<=w0^tem^rout1;
keyout[95 downto 64]<=w0^tem^rout1^w1;
keyout[63 downto 32]<=w0^tem^rout1^w1^w2;
keyout[31 downto 0]<=w0^tem^rout1^w1^w2^w3;
end Behavioral;
Error found is
ERROR:HDLParsers:164 - "D:/Files/newpro/keygeneration.vhd" Line 52. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK.
I have shown the 52nd line in the code. I have got the same error for all the assignment statements from line 52. Please help. Thanks in advance
2 errors:
VHDL does not use [] for indexing arrays (though they are used for signatures). Use () for indexing arrays instead.
There is no ^ operator in VHDL. Use xor instead.