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system-veriloghdl

Input Port Declaration with two sizes

I'm new to SystemVerilog and in the project I'm working on, I stumbled over the following port declaration. From VHDL I know the port declaration with one size (e.g. a 8-bit vector). But I don't understand why there are two sizes specified. Can someone explain it to me?

Thanks in advance!

module foobar
    #(parameter PORTS = 1)
     (input [PORTS-1:0][15:0] id_map);
endmodule
Solution

  • SystemVerilog has array datatypes with multiple dimensions (actually arrays of arrays) and allows ports to have array data types.

    An array is a fundamental data type in SystemVerilog and I suggest reading a number of tutorials on it. Here is one good explanation.