I am a newbie to VHDL and can't figure out how to debug VHDL code.
Is there any software that could probably give me an insight to the internal signals of my VHDL entity as time passes or something like that?
Please help.
As the other posts have pointed out, you'll likely need a simulator like GHDL. However, to debug your simulation, there are a few different methodologies:
Classic print statements -- just mix in writeline(output,[...]) in your procedural code. See this hello world example. If you're just getting started, then adding print statements will be invaluable. For most of the simulation debug that I do ( and that is part of my job ), I do almost all of the debug based on print statements that we've built up in our design and testbench. It is only for the final debug, or for more difficult issues that I use the next debug method.
"Dumping" the simulation ( for GHDL see this page and this one ). This is a cycle by cycle trace of your design ( or a subset of your design). It's as if you hook up a logic analyzer to every single wire in your design. All the info you could ever want about your design, but at a very low level -- the signal level. To use this methodology:
Create a simulation "dump". The base format for such a dump is a Value Change Dump or VCD. Whichever simulator you use, you'll need to read the documentation on how to create a VCD. ( You can also search "dump" in your docs -- your simulator may use a different file format for its dumps.)
Once you create a simulation dump, you then load your dump into a wave-form viewer. If you're using the gEDA package, then you would use gtkwave to view the dump.
note If you want to use GHDL and gtkwave to debug your VHDL code, you can install them on ubuntu with command:
% sudo apt-get install geda ghdl
( assuming you have root access to the machine running ubuntu)