Vivado doesn't recognize cell in EDIF file generated by Yosys

Question

I'm attempting to use Yosys to generate an edif file that I then use with Vivado tcl scripting to generate a bitstream for an Artix 7 (xc7a15t) FPGA. However, Vivado seems to have trouble with a few of the cells in the edif file.

When I use the same verilog and constraints file completely in Vivado the bitstream is created fine, and it works as expected when I load it onto the FPGA.

I've modeled my workflow off the example here.

Specifically, I'm using the following shell script as a frontend for the yosys and Vivado commands:

#!/bin/bash
yosys run_yosys.ys
vivado -nolog -nojournal -mode batch -source run_vivado.tcl

run_yosys.ys:

read_verilog top.v
synth_xilinx -edif top.edif -top top

run_vivado.tcl

read_xdc top.xdc
read_edif top.edif
link_design -part xc7a15tftg256-1 -top top
opt_design
place_design
route_design
report_utilization
report_timing
write_bitstream -force top.bit

top.v (simple blinky example):

`default_nettype none

module top (
            input wire clk,
            output reg led);

        reg [24:0]     cnt = 25'b0;

        always @(posedge clk) begin
                cnt <= cnt + 1'b1;
                if (cnt == 25'b0) begin
                        led <= !led;
                end
                else begin
                        led <= led;
                end
        end

endmodule // top

top.xdc:

create_clock -period 25.000 -name clk -waveform {0.000 12.500} [get_ports clk]

set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN N11} [get_ports clk]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN D1} [get_ports led]

set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

The Vivado tcl command opt_design generates the following error:

ERROR: [DRC INBB-3] Black Box Instances: Cell 'GND' of type 'GND/GND' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.

I get the same error for cell 'VCC'.

I also get a warning related to this when calling link_design:

CRITICAL WARNING: [Netlist 29-181] Cell 'GND' defined in file 'top.edif' has pin 'Y' which is not valid on primitive 'GND'.  Instance 'GND' will be treated as a black box, not an architecture primitive

Am I using Yosys incorrectly here? What's the correct flow for this? I'm new to Yosys, so forgive me if I've missed something obvious.

I'm using Yosys 0.8+147 and Vivado 2017.2

Answer 1

The solution is in the Yosys user manual. Vivado is complaining about the 'VCC' and 'GND' cells, so we must pass the -nogndvcc option to write_edif. As explained in the description for the -nogndvcc option, to do this we must use hilomap to associate VCC and GND with custom drivers. The full xilinx synthesis is achieved with:

synth_xilinx -top top
hilomap -hicell VCC P -locell GND G
write_edif -nogndvcc top.edif