How is computer with FPU classified in Flynn's taxonomy? If machine has a CPU with single core, but also has FPU, is that SISD or SIMD?
Is your FPU also a vector unit, or does one FPU instruction result in only one floating-point operation? (Or one FMA = 2 FLOPs; that would still be SISD because there's only one result, not multiple parallel results).
On many modern CPUs "the FPU" is short-hand for the hardware that includes the SIMD vector unit.
A single instruction will only trigger computation in the integer registers or the FPU; that's not SIMD. (Unless it's a SIMD vector instruction.)
Superscalar (multiple instructions per cycle) isn't SIMD either; and it's not even MIMD. The leading S refers to instruction streams, so finding and exploiting ILP to run multiple instructions per cycle from a single thread is not something that the taxonomy covers. (Besides SIMD width, it's the other major dimension of single-threaded performance, though.)