About data hazard and forwarding with beq in MIPS?

Question

Why the first add needs forwarding?

                    # stage:
add $1, $2, $3      # WB
add $4, $5, $6      # MEM
nop                 # EX
beq $1, $4, target  # ID

Since beq needs the $1, if the first add is about to execute WB-stage, isn't that no forwarding needed since beq at ID-stage, which is about to read the register file? My book says the second and third instruction before the beq will need forwarding to avoid data hazard.

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Edit: I found exactly what I meant on this link slide page 11; another slide that solves my another confusing that the first add isn't needed is by another technique special hardware, slide page 58.

Answer 1

In a synchronous digital system, during a cycle, there are two different phases. During the first phase, operands are read and transformed by means of operators. During the second phase, the resulting data are written to registers. Depending on the implementation,theses phases can correspond to the first and second half period, or to the complete period and the rising edge of the clock.

In either case, the important aspect is that it is possible to read (during the first phase) and to modify (at the end) the same register. This is why is is possible to do actions like

pc <= pc+4

in a single cycle.

In the problem that you raise, it is exactly what happens.

The action

  add $1, $2, $3      # WB

will read the pipeline register with the result during first phase and write is to $1 at the end of the cycle. while

 beq $1, $4, target  # ID

will read $1 and $4 during the first phase and write the result the ppline registers at the end of the cycle. Hence, without forwarding, it will be the previous value of $1 that will be written.

(edited according to comment below)

All these explainations are true is branch is dealt with standard HW. In that case comparison is done by the ALU at the "EX" stage and PC is updated at the end of this stage.

But this leads to a branch penalty of two cycles. To reduce this penalty, one can add HW to perform the comparison at the ID stage. In that case, if the comparison requires a value been computed (as $1 in your example), a stall will be required.