two different errors in modelsim when '=' or '<=' used

I'm learning VHDL, and I've been struggling with this simple example below since yesterday.

Write an entity in VHDL for a zero (0) to nine (9) counter, triggered by a positive edge clock and has an asynchronous active high 'reset to zero' input. The system has three (3) output signals 'LOW' 'MID' and 'HIGH' that generate the following values:

Assume that all signals are of type Std_logic.

The code is like this;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY LMHcounter IS
  PORT(clk,reset:in std_logic; 
    L:out std_logic; 
    M:out std_logic; 
    H:out std_logic);
END LMHcounter;

ARCHITECTURE behavior OF UPcounter IS
SIGNAL count:std_logic_vector(3 downto 0);

BEGIN
PROCESS(clk,reset)
BEGIN
   if reset='1' then count<="0000";
   elsif (rising_edge(clk))then 
    if count<="1001" then
         count<="0000";
    else count<=count+"0001";
    end if;
   end if;

END PROCESS;
L<='1' when count<="0101"; 
    else '0';
M<='1' when count="0110"; 
    else '0';
H<='1' when count>="0111"; 
    else '0';


END behavior;

If I use L='1' at the end I get;

 Error: C:/DL_Project/LMH Counter.vhd(29): near "=": (vcom-1576) expecting == or '+' or '-' or '&'.

If I use L<='1' at the end I get;

Error: C:/DL_Project/LMH Counter.vhd(29): Illegal target for signal assignment.
Error: C:/DL_Project/LMH Counter.vhd(29): (vcom-1136) Unknown identifier "L".

Error: C:/DL_Project/LMH Counter.vhd(30): near "else": (vcom-1576) expecting END.

I can't use ':=' as apparently modelsim does not support

Error: C:/DL_Project/LMH Counter.vhd(29): (vcom-1441) CONDITIONAL VARIABLE ASSIGNMENT is not defined for this version of the language.

** Error: C:/DL_Project/LMH Counter.vhd(30): near "else": (vcom-1576) expecting END.

I'm sure it's trivial, but I can't seem to find an answer anywhere. And also can someone explain please what is happening in the background if I use '=' or '<='?

Thanks

Solution

There are quite a few errors i found,

Firstly, you are trying to describe an architecture for a different entity other than the one you declared. I guess that should be ARCHITECTURE behavior OF LMHcounterIS instead of ARCHITECTURE behavior OF UPcounter IS
The syntax for the conditional signal assignment is wrong, you should use it as signal <= [expression when condition else ...] expression;. In your code that should be
```
L<='1' when count<="0101" else '0';
M<='1' when count="0110"  else '0';
H<='1' when count>="0111" else '0';
```