I am coding a FSM in VHDL. In particular it is a synchronized sequence detector that has in input a number on 8 bit and a "first", that has to be '1' only during the first number of the sequence. The output is composed by an unlock and warning: unlock = '1' if the sequence (36, ...) was right, or warning = '1' if the sequence was wrong or first = '1' not during the first number of the sequence.
In VHDL I use two processes, one synchronized and one not. The simplified version of the second is:
state_register_p : process(clk)
begin
if (clk'EVENT and clk = '1') then
if(rst = '0') then
current_state <= S0;
errors_num <= "00";
five_cycles <= "000";
first_error <= '1';
else
current_state <= next_state;
if correct = '0' then
errors_num <= errors_num + "01";
else
errors_num <= "00";
end if;
end if;
end if;
end process state_register_p;
combinatorial_logic_p : process(current_state, num_in, first)
begin
unlock <= '0';
warning <= '0';
case (current_state) is
when S0 =>
if (to_integer(unsigned(num_in)) = 36) and (first = '1') then
next_state <= S1;
else
next_state <= S0;
when S1 =>
correct <= '0';
if (to_integer(unsigned(num_in)) = 19) and (first = '0') and errors_num /= "11" then
next_state <= S2;
elsif first = '1' or errors_num = "11" then
next_state <= S6;
else
next_state <= S0;
end if;
when S2 =>
correct <= '0';
if (to_integer(unsigned(num_in)) = 56) and (first = '0') then
next_state <= S3;
elsif first = '1' then
next_state <= S6;
else
next_state <= S0;
end if;
when S3 =>
correct <= '0';
if (to_integer(unsigned(num_in)) = 101) and (first = '0') then
next_state <= S4;
elsif first = '1' then
next_state <= S6;
else
next_state <= S0;
end if;
when S4 =>
correct <= '0';
if (to_integer(unsigned(num_in)) = 73) and (first = '0') and (to_integer(unsigned(five_cycles)) = 5) then
next_state <= S5;
correct <= '1';
elsif first = '1' then
next_state <= S6;
else
next_state <= S0;
end if;
when S5 =>
correct <= '1';
if to_integer(unsigned(num_in)) = 36 and (first = '1') then
next_state <= S1;
else
next_state <= S0;
end if;
unlock <= '1';
when S6 =>
correct <= '0';
next_state <= S6; -- default, hold in current state
warning <= '1';
end case;
end process combinatorial_logic_p;
By reading online I know that in a Moore machine the next state depends on the current state only so the outputs only change on clock edges, while in Mealy it depends also on the input so its outputs may change when an input changes (i.e., not necessarily on a clock edge). .
In my sensitivity list I use current_state and 2 inputs (num_in and first), so is it possible to say that I am describing a Mealy machine or is it still a Moore machine because I am waiting the next rising edge to update the output?
I still think it is Moore, but I am not sure. Thanks
It is a Moore state machine, since the outputs unlock and warning depend only on current_state in the combinatorial_logic_p process.
Note that the signals errors_num and five_cycles are used in the combinatorial_logic_p process, but forgotten in the sensitivity list. So add them, or change to (all) if using VHDL-2008.