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verilogsynthesisxilinx-isesynplify

Synopsys Synplify Pro synthesis failed when using "``"

When I try to use construction like this my synthesis was failed

`define defLOMIC 0 //For example
`define rd(LOMIC) `def``LOMIC

Late:

wire lod = `rd(LOMIC);

Error:

E   CS231   Unknown macro def   VDF_TOP.v (368) syntax.log (13) 09:14:32 Thu Dec 06 Synthesis Check
E   CS234   expecting identifier immediately following back-quote (`)   VDF_TOP.v (368) syntax.log (14) 09:14:32 Thu Dec 06 Synthesis Check

If I use ISE XST for this, the synthesis goes well.

Used "Synplify C-2009.06"

Does anyone know maybe "``" is not supported? How to enable it? Or in which version is support it?

Solution

  • '``' is a SystemVerilog construct. Change your file extension to *.sv. Or use the -sysv switch. It's possible 2009 is too old a version.