VHDL (Error (10500): VHDL syntax error at Router.vhd(39) near text "port"; expecting "(", or "'", or ".")

Question

So basically I am doing the Mousetrap Latch controller on Altera and the syntax error keeps showing up (Error (10500): VHDL syntax error at Router.vhd(39) near text "port"; expecting "(", or "'", or ".").

    Library ieee; 
    use ieee.std_logic_1164.all; 
    use ieee.std_logic_arith.all; 
    use ieee.std_logic_signed.all; 

    entity Router is
    port(Ri, Ao, vld_i, rst: in std_logic; Data_i: in std_logic_vector(33 
    downto 0); Ro, Ai, vld_o: out std_logic; 
    Data_o: out std_logic_vector(33 downto 0));
    end entity Router;

    architecture behavioral of Router is
    signal reqI, ackO, VLDi: std_logic;
    signal reqO, VLDo: std_logic;
    signal Di, Do : std_logic_vector (33 downto 0);
    component latch1
    port(D, en: in std_logic; Q: out std_logic);
    end component;

    component latch_34
    port(D: in std_logic_vector(33 downto 0); en: in std_logic; Q: out 
    std_logic_vetor(33 downto 0));
    end component;
    begin

    process (rst)
    begin
    reqI<= Ri;
    ackO<= Ao;
    VLDi<=vld_i;
    Di<= Data_i;
    if (rst ='1') then
    reqI <= "0";
    ackO<='0';
    VLDi<='0';
    Di<= '0';
    Do<= '0';
    reqO<= '0';
    VLDo<= '0';
    else
    **u1: latch1 port map(reqI<=reqI, en<=reqO XNOR ackO, reqO<=reqO);**
    **u2: latch1 port map(VLDi, reqO XNOR ackO, VLDo);**
    **u3: latch_34 port map(Di, Not(reqO XNOR ackO) NAND VLDo, Do);**
    end if;
    end process;
    Ro<=reqO;
    Ai<=reqO;
    vld_o<= VLDo;
    Do<=Data_o;
    end behavioral;

Answer 1

You forgot a "c" in std_logic_vector :

component latch_34
port(D: in std_logic_vector(33 downto 0); en: in std_logic; Q: out 
std_logic_vetor(33 downto 0));
end component;