How to assign a value to a sliced output signal?

Question

I'm a beginner with myhdl. I try to translate the following Verilog code to MyHDL:

module ModuleA(data_in, data_out, clk);
    input data_in;
    output reg data_out;
    input clk;

    always @(posedge clk) begin
        data_out <= data_in;
    end
endmodule

module ModuleB(data_in, data_out, clk);
    input [1:0] data_in;
    output [1:0] data_out;
    input clk;

    ModuleA instance1(data_in[0], data_out[0], clk);
    ModuleA instance2(data_in[1], data_out[1], clk);
endmodule

Currently, I have this code:

import myhdl

@myhdl.block
def ModuleA(data_in, data_out, clk):
    @myhdl.always(clk.posedge)
    def logic():
        data_out.next = data_in

    return myhdl.instances()


@myhdl.block
def ModuleB(data_in, data_out, clk):
    instance1 = ModuleA(data_in(0), data_out(0), clk)
    instance2 = ModuleA(data_in(1), data_out(1), clk)

    return myhdl.instances()


# Create signals
data_in = myhdl.Signal(myhdl.intbv()[2:])
data_out = myhdl.Signal(myhdl.intbv()[2:])
clk = myhdl.Signal(bool())

# Instantiate the DUT
dut = ModuleB(data_in, data_out, clk)

# Convert tfe DUT to Verilog
dut.convert()

But it doesn't works because signal slicing produce a read-only shadow signal (cf MEP-105). So, what is it the good way in MyHDL to have a writable slice of a signal?

Edit: This is the error I get

$ python demo.py
Traceback (most recent call last):
File "demo.py", line 29, in <module>
    dut.convert()
File "/home/killruana/.local/share/virtualenvs/myhdl_sandbox-dYpBu4o5/lib/python3.6/site-packages/myhdl-0.10-py3.6.egg/myhdl/_block.py", line 342, in convert
File "/home/killruana/.local/share/virtualenvs/myhdl_sandbox-dYpBu4o5/lib/python3.6/site-packages/myhdl-0.10-py3.6.egg/myhdl/conversion/_toVerilog.py", line 177, in __call__
File "/home/killruana/.local/share/virtualenvs/myhdl_sandbox-dYpBu4o5/lib/python3.6/site-packages/myhdl-0.10-py3.6.egg/myhdl/conversion/_analyze.py", line 170, in _analyzeGens
File "/usr/lib/python3.6/ast.py", line 253, in visit
    return visitor(node)
File "/home/killruana/.local/share/virtualenvs/myhdl_sandbox-dYpBu4o5/lib/python3.6/site-packages/myhdl-0.10-py3.6.egg/myhdl/conversion/_analyze.py", line 1072, in visit_Module
File "/home/killruana/.local/share/virtualenvs/myhdl_sandbox-dYpBu4o5/lib/python3.6/site-packages/myhdl-0.10-py3.6.egg/myhdl/conversion/_misc.py", line 148, in raiseError
myhdl.ConversionError: in file demo.py, line 4:
    Signal has multiple drivers: data_out

Answer 1

You can use an intermediate list of Signal(bool()) as placeholder.

@myhdl.block
def ModuleB(data_in, data_out, clk):
    tsig = [myhdl.Signal(bool(0)) for _ in range(len(data_in))]

   instances = []
   for i in range(len(data_in)):
        instances.append(ModuleA(data_in(i), tsig[i], clk))

   @myhdl.always_comb
   def assign():
        for i in range(len(data_out)):
            data_out.next[i] = tsig[i]

   return myhdl.instances()