How to cover a fifo rd/wt property?

Question

I am trying to write a fifo rd write cover point.

module M;

  bit stop;  bit clk; initial while (!stop) #5 clk = ~clk;

  bit A, B, rst;

  initial rst = 0;

  initial begin
    A = 0;
    #20 A = 1;
    #10 A = 0;
    // #10 B = 1;
    #10 B = 0;
    #50 stop = 1;
  end


  // sequence fifo_rd_wt_s(reg sig);
  //  ((|A === 1) |-> s_eventually (|B === 1));
  // endsequence: fifo_rd_wt_s

  property fifo_rd_wt_p(reg sig_clk, reg sig_rst);
    @(posedge sig_clk) disable iff(sig_rst)
    ((|A === 1) |-> s_eventually (|B === 1));
  endproperty: fifo_rd_wt_p


  cover_fifo_read_write: cover property(fifo_rd_wt_p(clk, rst)) $error($sformatf("%0t hit fifo read write", $time)); 
      // else $error($sformatf("%0t did not hit", $time));



   final
     $display("Finished!");

endmodule: M

In the run log I see that it is getting triggered every cycle, but that is not what I want. I want it to trigger every time it sees a A followed by a B.

Not sure what I am missing.

I found something similar here

The code is present in code

Answer 1

I think your issue is with the implication. I used your example and replaced with strong((|A === 1) ##[1:$] (|B === 1)); it was working fine.

Cover with implication can have some unexpected behavior (in your case it was covering the antecedent), it s always safer to use cover with sequences