What's the purpose of clocked registers in pipelined processor

Question

Hi I'm reading an textbook that descrbes the piplelined desgin of CPU. I don't understand why we still need clocked registers? for example, as the picture belows shows:

if we can remove all three registers, we can save 60ps, because we just need the processor to continuely execute instructions, so when a comb logic finishes, that's when the next instruction should start to execute, why we need clock cycle to manually control the beginning of executing instructions?

Answer 1

You can begin to understand the need for latches by imagining that they are removed.

The secret is to realize that it takes each block 100 picoseconds to produce valid results. Before that time, the output is invalid, aka junk and not as you might think, the previous result. Remember, these a combinatorial blocks that have no memory.

Now imagine that we place new data on the inputs of Block A every 100 picoseconds.

What will the output look like? Well as soon as the new data is presented to the inputs, the outputs of that block are invalid. This means that Block B has invalid inputs and cannot begin processing data until they are valid.

Now after 100 picoseconds, Block A has valid data going out and Block B can finally begin. But no, the input to Block A changes and Block B has invalid inputs again. The only way to get a valid result through all three is to hold the inputs valid for the whole 300 picoseconds needed to get through all three blocks.

With latches, the valid results from each block are latched and do not change with changing inputs. Thus we can present new data every 100 + 20 picoseconds versus every 300 picoseconds. Or, with pipeline latches the circuit runs 2.5 times faster.