I am writing a Testbench using Systemverilog and I want to have the freedom to choose in each test to either randomize some variables or specify their value (from a .do file or from command line). Is there any option in Systemverilog to do this?
There are many things you can do, but the simplest is putting +some_variable=value
on the command line, and then in your code
if (!$value$plusargs("some_variable=%0d",some_variable)
some_variable = $urandom;