I only need to modify a source code for just another port/pins. I have studied with NXP UM10360 as much as I could.
I have that setup;
Header file used from "CMSIS_CORE_LPC17xx" : LPC17xx.h
LPC_PINCON->PINSEL0 |= 0x2<<14; //P0.7 > SCK1
LPC_PINCON->PINSEL0 |= 0x2<<16; //P0.8 > MISO1
LPC_PINCON->PINSEL0 |= 0x2<<18; //P0.9 > MOSI1
and
I want to replace those pins with another (from SSP1 to SSP0).
P0.7 will be P0.15
P0.8 will be P0.17
P0.9 will be P0.18
And as per the manual, I tried this (Function 10);
LPC_PINCON->PINSEL0 &= ~((0x3 << 31)|(0x3 << 30));//P0.15, SCK0
LPC_PINCON->PINSEL0 |= ((0x2 << 31)|(0x2 << 30)); //ENable clock
LPC_PINCON->PINSEL1 &= ~((0x2 << 3)|(0x2 << 2));//P0.17, MISO0
LPC_PINCON->PINSEL1 &= ~((0x2 << 5)|(0x2 << 4));//P0.18, MOSI0
But, SPI device has stopped after this. The original setup above is working fine and showing me nice SPI signals with Logic Analyzer. But, with that new pins and setup accordingly, I can only get CSN and MISO and SCK only enabled (no pulse) on the Logic Analyzer.
Just this:
What am I doing wrong? (I am inexperienced with NXP MCU's, please bear with me.)
Edited:
For the records, I found it my-self eventually, problem solved;
LPC_PINCON->PINSEL0 |= 0x2<<30; //SCK0, P0.15
LPC_PINCON->PINSEL1 |= 0x2<<2; //MISO0, P0.17
LPC_PINCON->PINSEL1 |= 0x2<<4; //MOSI0, P0.18
LPC_GPIO0->FIODIR |= (1<<16); //SSEL/CSN, P0.16
Here is the outcome on the Logic Analyzer;
For the records, I could manage to setup a working solution just by setting up that way;
LPC_PINCON->PINSEL0 |= 0x2<<30; //SCK0, P0.15
LPC_PINCON->PINSEL1 |= 0x2<<2; //MISO0, P0.17
LPC_PINCON->PINSEL1 |= 0x2<<4; //MOSI0, P0.18
LPC_GPIO0->FIODIR |= (1<<16); //SSEL/CSN, P0.16