How to assign one bit of std_logic_vector to 1 and others to 0

Question

I'm receiving from outside std_logic_vector with binary value, that is represent the bit which should be set to one and others to 0. As I understand it's decoder, but solving this problem with "when" statement will take so much lines of the code, plus it isn't reconfigurable.

Example:

signal number : std_logic_vector(7 downto 0); 
signal output : std_logic_vector(255 downto 0);

output <= output(to_integer(unsigned(number))) and (others=>'0');

Answer 1

There are many ways to do this. All (syntactically and semantically valid) ways can be simulated. Some can be synthesized, some cannot but as this depends on your synthesizer it is difficult to say. First, let's rename output to result: output is not a key word of the VHDL language but it is the name of the standard output stream defined in the std.textio package. It is thus better to avoid using it as a user identifier.

1. Process with variable and addressed bits (exercise: study the aggregate notation and understand (others => '0')):

   process(number)
       variable tmp: std_logic_vector(255 downto 0);
   begin
       tmp := (others => '0');
       tmp(to_integer(unsigned(number))) := '1';
       result <= tmp;
   end process;
   

2. Equivalent without the intermediate variable (exercise: study signal assignments and understand why it works):

   process(number)
   begin
       result <= (others => '0');
       result(to_integer(unsigned(number))) <= '1';
   end process;
   

3. Process with barrel shifter in VHDL 2002 (possibly still not supported by your tools):

   architecture foo of bar is
       ...
       constant one: std_logic_vector(255 downto 0) := (0 => '1', others => '0');
       ...
   begin
       ...
       process(number)
       begin
           result <= one sll to_integer(unsigned(number));
       end process;
       ...
   end architecture foo;
   

4. Concurrent signal assignment with barrel shifter in VHDL 2002 (exercise: understand that concurrent signal assignments are processes, imagine the equivalent process):

   architecture foo of bar is
       ...
       constant one: std_logic_vector(255 downto 0) := (0 => '1', others => '0');
       ...
   begin
       ...
       result <= one sll to_integer(unsigned(number));
       ...
   end architecture foo;