I am studying some techniques to reduce power in digital circuits, and one way was to reduce the applied voltage but the trade off is the delay of the circuit will increase, I would appreciate if someone could explain how the delay is related to the voltage applied.
Every transistor has some capacitance at the gate, this is unavoidable. When you apply a voltage to it in order to trigger the transistor, you need to wait for that "capacitor" to charge. The higher the voltage you apply in relation to the trigger voltage, the faster it'll change and so the faster it'll change its state.
TL;DR lower voltage makes transistors change their state slower due to gate capacitance.